1. Field
The invention is related to voltage clamps and, more particularly, to voltage clamps for input/output port or pad protection.
2. Background Information
As is well-known, operating voltages for integrated circuit components and integrated circuit chips continue to decline. One disadvantage of this decline in operating voltages is that legacy devices and/or systems that operate at these legacy voltage levels maintain voltage signal levels at high voltages compared to the voltage signal levels for native process technology, which continues to decline approximately 30% per generation. Therefore, it is desirable to devise circuit techniques or other approaches to allow backwards compatibility for one generation, or even more, of fabrication process technology. For example, state-of-the-art fabrication process technology is on the order of approximately 1.8 volts, although legacy operating voltages may be at about 3.3 volts. Therefore, voltage excursions from this operating voltage, such as may occur at a pad of an integrated circuit, for example, or at a pin or port, may damage transistors fabricated using native process technology, but being applied in circuit environments employing legacy operating voltages. A need exists for techniques to handle these legacy operating voltages using native process technology and/or reduce the damage that may occur from voltage excursions.
Briefly, in accordance with one embodiment of the invention, an integrated circuit comprises: a bias voltage source. The bias voltage source is coupled to a pad of the integrated circuit so as to clamp the pad voltage to the bias voltage when, during circuit operation, the voltage of the pad exceeds an upper voltage rail of the integrated circuit.